Lab Engineer - DSP Engineer (Hardware)
Last Date: Sunday, November 9, 2014  
Job Detail   
Job Ref #: Job/1854/10/17/2014
 Age Limit: 20  - 45
Experience:
Posted Date: Friday, October 17, 2014
Salary:
Job Description:
BE Electrical/Computer with 1-2 years’ experience in RTL design for Xilinx FPGAs. Fresh graduates with strong RTL design concepts are also encouraged to apply.

Note:   Students of MS will not be considered for employment as Lab Engineer.